We use www.tanner.com/eda tools for our chip design and have learned a number of useful tricks. These are for version 12x.

• When doing extract of a large array, populate just the rim with circuits (e.g. pixels), ensuring full generality of course, and simplify the wiring of the dummy connection cells as much as possible, e.g. just metal wires and no diffusion or wells.
• Use an extract bin size that is the same as the pixel pitch - this seems to increase cache reuse.
• Don't label devices, and use numbers for nodes rather than names (string handling seems to slow down extract a lot).
• We need at least version 12.5 for our extract which is based on partial Calibre setup to run. Version 12.1 complains about derived layers not being defined but we haven't figured out why.
• We use a machine at the lab with the hardware dongle on it as the extraction server and connect to it via gotomypc or vnc for extraction.
• We use subversion for all our project management. We split the layout and schematics into libraries so that we can separately work on parts of the chip designs.
• For DRC, try to draw your cells so they really DRC clean without being arrayed. Tanner's HiPer DRC doesn't understand that subcells DRC ok when arrayed and complains endlessly about cells with half contacts. Use the Icon/Abut layer (which you can define) to enable alignment of cells with layout sticking out of the abut bounding box.
• Starting with Tanner 12.5, you can create or stretch arrays by drag-editing the corners or edges of an instance. The problem is that this makes it hard to use the handy snap-alignment tools to align your cells (e.g. pads). To avoid editing array sizes, use “Force Move” (map this to a keyboard shortcut).
• Be really careful about properly gridding your schematics, especially if they are migrated from earlier (prev version 12) of Tanner's S-Edit. Once your design goes “off-grid” you are in big trouble. S-Edit has a tool that computes the maximum possible grid, but this will be ridulously small if your have a mix of grids.
• Schematics migrated from earlier S-Edit versions sometimes have little boxes drawn on the terminals of devices like FETS. These cause terrible off-grid hassles if they are rotated because they throw the pins off-grid. Get rid of these left-over terminal boxes.
• We've had lots of trouble with dropped schematic connections. These seem be related to funny gridding in a design. Don't let anyone on your design team go off grid!