| HelloWorldSynchronous_Lab3 Project Status (08/28/2009 - 18:59:31) | |||
| Project File: | HelloWorldSynchronous_Lab3.ise | Implementation State: | Programming File Generated |
| Module Name: | HelloSynchronousWorld |
|
No Errors |
| Target Device: | xc3s100e-4cp132 |
|
1 Warning (0 new) |
| Product Version: | ISE 11.2 |
|
All Signals Completely Routed |
| Design Goal: | Balanced |
|
All Constraints Met |
| Design Strategy: | Xilinx Default (unlocked) |
|
0 (Setup: 0, Hold: 0) (Timing Report) |
| Device Utilization Summary | [-] | ||||
| Logic Utilization | Used | Available | Utilization | Note(s) | |
| Number of Slices containing only related logic | 0 | 0 | 0% | ||
| Number of Slices containing unrelated logic | 0 | 0 | 0% | ||
| Number of bonded IOBs | 4 | 83 | 4% | ||
| IOB Flip Flops | 2 | ||||
| Number of BUFGMUXs | 1 | 24 | 4% | ||
| Average Fanout of Non-Clock Nets | 1.00 | ||||
| Performance Summary | [-] | |||
| Final Timing Score: | 0 (Setup: 0, Hold: 0) | Pinout Data: | Pinout Report | |
| Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
| Timing Constraints: | All Constraints Met | |||
| Detailed Reports | [-] | |||||
| Report Name | Status | Generated | Errors | Warnings | Infos | |
| Synthesis Report | Current | Fri 28. Aug 18:40:04 2009 | 0 | 0 | 0 | |
| Translation Report | Current | Fri 28. Aug 18:57:50 2009 | 0 | 0 | 0 | |
| Map Report | Current | Fri 28. Aug 18:58:03 2009 | 0 | 0 | 2 Infos (0 new) | |
| Place and Route Report | Current | Fri 28. Aug 18:58:53 2009 | 0 | 1 Warning (0 new) | 2 Infos (0 new) | |
| Power Report | ||||||
| Post-PAR Static Timing Report | Current | Fri 28. Aug 18:59:04 2009 | 0 | 0 | 3 Infos (0 new) | |
| Bitgen Report | Current | Fri 28. Aug 18:59:13 2009 | 0 | 0 | 0 | |
| Secondary Reports | [-] | ||
| Report Name | Status | Generated | |
| ISIM Simulator Log | Out of Date | Fri 28. Aug 18:34:50 2009 | |