| HelloLotsofWorlds_Lab2 Project Status (08/28/2009 - 17:48:45) | |||
| Project File: | HelloLotsofWorlds_Lab2.ise | Implementation State: | Programming File Generated |
| Module Name: | HelloLotsofWorlds |
|
No Errors |
| Target Device: | xc3s100e-4cp132 |
|
No Warnings |
| Product Version: | ISE 11.2 |
|
All Signals Completely Routed |
| Design Goal: | Balanced |
|
|
| Design Strategy: | Xilinx Default (unlocked) |
|
0 (Setup: 0, Hold: 0) (Timing Report) |
| Device Utilization Summary | [-] | ||||
| Logic Utilization | Used | Available | Utilization | Note(s) | |
| Number of Slices containing only related logic | 0 | 0 | 0% | ||
| Number of Slices containing unrelated logic | 0 | 0 | 0% | ||
| Number of bonded IOBs | 16 | 83 | 19% | ||
| Average Fanout of Non-Clock Nets | 1.00 | ||||
| Performance Summary | [-] | |||
| Final Timing Score: | 0 (Setup: 0, Hold: 0) | Pinout Data: | Pinout Report | |
| Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
| Timing Constraints: | ||||
| Detailed Reports | [-] | |||||
| Report Name | Status | Generated | Errors | Warnings | Infos | |
| Synthesis Report | Current | Fri 28. Aug 17:45:59 2009 | 0 | 0 | 0 | |
| Translation Report | Current | Fri 28. Aug 17:47:21 2009 | 0 | 0 | 0 | |
| Map Report | Current | Fri 28. Aug 17:47:33 2009 | 0 | 0 | 2 Infos (0 new) | |
| Place and Route Report | Current | Fri 28. Aug 17:48:13 2009 | 0 | 0 | 2 Infos (0 new) | |
| Power Report | ||||||
| Post-PAR Static Timing Report | Current | Fri 28. Aug 17:48:23 2009 | 0 | 0 | 3 Infos (0 new) | |
| Bitgen Report | Current | Fri 28. Aug 17:48:31 2009 | 0 | 0 | 0 | |
| Secondary Reports | [-] | ||
| Report Name | Status | Generated | |