| Project Statistics |
| PROP_Synthesis_Tool=XST (VHDL/Verilog) |
PROP_Simulator=ISim (VHDL/Verilog) |
| PROP_Top_Level_Module_Type=HDL |
PROP_PreferredLanguage=Verilog |
| PROP_Enable_Message_Filtering=false |
PROP_Enable_Incremental_Messaging=false |
| PROP_UseSmartGuide=false |
Partitions count=1 |
| FILE_UCF=1 |
FILE_VERILOG=2 |
| PROP_DevFamily=Spartan3E |
PROP_DevPackage=cp132 |
| PROP_DevSpeed=-4 |
PROP_FitterReportFormat=HTML |
| PROP_Simulator=ISim (VHDL/Verilog) |
PROP_UserConstraintEditorPreference=Constraints Editor |
| PROP_lockPinsUcfFile=changed |
Project duration(days)=0 |