StateMachineWorldTOP Project Status (09/01/2009 - 00:42:55)
Project File: WorldofStateMachines_Lab11.xise Parser Errors:
Module Name: StateMachineWorldTOP Implementation State: Programming File Generated
Target Device: xc3s100e-4cp132
  • Errors:
No Errors
Product Version:ISE 13.4
  • Warnings:
No Warnings
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 3 1,920 1%  
Number of 4 input LUTs 17 1,920 1%  
Number of occupied Slices 9 960 1%  
    Number of Slices containing only related logic 9 9 100%  
    Number of Slices containing unrelated logic 0 9 0%  
Total Number of 4 input LUTs 17 1,920 1%  
Number of bonded IOBs 17 83 20%  
Number of BUFGMUXs 1 24 4%  
Average Fanout of Non-Clock Nets 3.83      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentMon Aug 31 23:44:40 2009000
Translation ReportCurrentMon Aug 31 23:45:02 2009000
Map ReportCurrentMon Aug 31 23:45:18 2009002 Infos (0 new)
Place and Route ReportCurrentMon Aug 31 23:46:10 2009004 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentMon Aug 31 23:46:22 2009003 Infos (0 new)
Bitgen ReportCurrentMon Aug 31 23:46:32 2009000
 
Secondary Reports [-]
Report NameStatusGenerated

Date Generated: 05/25/2012 - 15:40:05