| StateMachineWorldTOP Project Status (09/01/2009 - 00:42:55) | |||
| Project File: | WorldofStateMachines_Lab11.xise | Parser Errors: | |
| Module Name: | StateMachineWorldTOP | Implementation State: | Programming File Generated |
| Target Device: | xc3s100e-4cp132 |
|
No Errors |
| Product Version: | ISE 13.4 |
|
No Warnings |
| Design Goal: | Balanced |
|
All Signals Completely Routed |
| Design Strategy: | Xilinx Default (unlocked) |
|
All Constraints Met |
| Environment: | System Settings |
|
0 (Timing Report) |
| Device Utilization Summary | [-] | ||||
| Logic Utilization | Used | Available | Utilization | Note(s) | |
| Number of Slice Flip Flops | 3 | 1,920 | 1% | ||
| Number of 4 input LUTs | 17 | 1,920 | 1% | ||
| Number of occupied Slices | 9 | 960 | 1% | ||
| Number of Slices containing only related logic | 9 | 9 | 100% | ||
| Number of Slices containing unrelated logic | 0 | 9 | 0% | ||
| Total Number of 4 input LUTs | 17 | 1,920 | 1% | ||
| Number of bonded IOBs | 17 | 83 | 20% | ||
| Number of BUFGMUXs | 1 | 24 | 4% | ||
| Average Fanout of Non-Clock Nets | 3.83 | ||||
| Performance Summary | [-] | |||
| Final Timing Score: | 0 (Setup: 0, Hold: 0) | Pinout Data: | Pinout Report | |
| Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
| Timing Constraints: | All Constraints Met | |||
| Detailed Reports | [-] | |||||
| Report Name | Status | Generated | Errors | Warnings | Infos | |
| Synthesis Report | Current | Mon Aug 31 23:44:40 2009 | 0 | 0 | 0 | |
| Translation Report | Current | Mon Aug 31 23:45:02 2009 | 0 | 0 | 0 | |
| Map Report | Current | Mon Aug 31 23:45:18 2009 | 0 | 0 | 2 Infos (0 new) | |
| Place and Route Report | Current | Mon Aug 31 23:46:10 2009 | 0 | 0 | 4 Infos (0 new) | |
| Power Report | ||||||
| Post-PAR Static Timing Report | Current | Mon Aug 31 23:46:22 2009 | 0 | 0 | 3 Infos (0 new) | |
| Bitgen Report | Current | Mon Aug 31 23:46:32 2009 | 0 | 0 | 0 | |
| Secondary Reports | [-] | ||
| Report Name | Status | Generated | |