Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 

 
Software Version and Target Device
Product Version: ISE:14.4 (ISE) - P.49d Target Family: Spartan3E
OS Platform: NT Target Device: xc3s100e
Project ID (random number) b85c5854cbb64ce99b7e2b9e3a74d5ae.7541A142F1754D2DA8C1E4A280B88218.1 Target Package: cp132
Registration ID 205868839_205625405_210133127_560 Target Speed: -4
Date Generated 2013-05-10T11:34:53 Tool Flow ISE
 
User Environment
OS Name Microsoft Windows 7 , 64-bit OS Release Service Pack 1 (build 7601)
CPU Name Intel(R) Core(TM) i7 CPU 975 @ 3.33GHz CPU Speed 3340 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Counters=2
  • 25-bit updown counter=1
  • 8-bit updown counter=1
MiscellaneousStatistics
  • AGG_BONDED_IO=12
  • AGG_IO=12
  • AGG_SLICE=39
  • NUM_4_INPUT_LUT=73
  • NUM_BONDED_IBUF=4
  • NUM_BONDED_IOB=8
  • NUM_BUFGMUX=1
  • NUM_CYMUX=31
  • NUM_SLICEL=39
  • NUM_SLICE_FF=33
  • NUM_XOR=33
NetStatistics
  • NumNets_Active=105
  • NumNets_Vcc=1
  • NumNodesOfType_Active_CLKPIN=18
  • NumNodesOfType_Active_CNTRLPIN=36
  • NumNodesOfType_Active_DOUBLE=137
  • NumNodesOfType_Active_DUMMY=199
  • NumNodesOfType_Active_DUMMYESC=4
  • NumNodesOfType_Active_GLOBAL=11
  • NumNodesOfType_Active_HUNIHEX=4
  • NumNodesOfType_Active_INPUT=224
  • NumNodesOfType_Active_IOBOUTPUT=4
  • NumNodesOfType_Active_OMUX=83
  • NumNodesOfType_Active_OUTPUT=89
  • NumNodesOfType_Active_PREBXBY=46
  • NumNodesOfType_Active_VFULLHEX=2
  • NumNodesOfType_Active_VUNIHEX=1
  • NumNodesOfType_Vcc_CNTRLPIN=1
  • NumNodesOfType_Vcc_VCCOUT=1
SiteStatistics
  • IBUF-DIFFM=1
  • IBUF-DIFFMI=1
  • IOB-DIFFM=2
  • IOB-DIFFS=5
  • SLICEL-SLICEM=16
SiteSummary
  • BUFGMUX=1
  • BUFGMUX_GCLKMUX=1
  • BUFGMUX_GCLK_BUFFER=1
  • IBUF=4
  • IBUF_INBUF=4
  • IBUF_PAD=4
  • IOB=8
  • IOB_OUTBUF=8
  • IOB_PAD=8
  • SLICEL=39
  • SLICEL_CYMUXF=16
  • SLICEL_CYMUXG=15
  • SLICEL_F=39
  • SLICEL_FFX=17
  • SLICEL_FFY=16
  • SLICEL_G=34
  • SLICEL_XORF=17
  • SLICEL_XORG=16
 
Configuration Data
BUFGMUX
  • S=[S_INV:1] [S:0]
BUFGMUX_GCLKMUX
  • DISABLE_ATTR=[LOW:1]
  • S=[S_INV:1] [S:0]
IBUF_PAD
  • IOATTRBOX=[LVCMOS25:4]
IOB
  • O1=[O1_INV:0] [O1:8]
IOB_OUTBUF
  • IN=[IN_INV:0] [IN:8]
IOB_PAD
  • DRIVEATTRBOX=[12:8]
  • IOATTRBOX=[LVCMOS25:8]
  • SLEW=[SLOW:8]
SLICEL
  • BX=[BX_INV:2] [BX:0]
  • CE=[CE:18] [CE_INV:0]
  • CIN=[CIN_INV:0] [CIN:15]
  • CLK=[CLK:18] [CLK_INV:0]
  • SR=[SR:18] [SR_INV:0]
SLICEL_CYMUXF
  • 0=[0:16] [0_INV:0]
  • 1=[1_INV:2] [1:14]
SLICEL_CYMUXG
  • 0=[0:15] [0_INV:0]
SLICEL_FFX
  • CE=[CE:17] [CE_INV:0]
  • CK=[CK:17] [CK_INV:0]
  • D=[D:17] [D_INV:0]
  • FFX_INIT_ATTR=[INIT0:17]
  • FFX_SR_ATTR=[SRLOW:17]
  • LATCH_OR_FF=[FF:17]
  • SR=[SR:17] [SR_INV:0]
  • SYNC_ATTR=[SYNC:17]
SLICEL_FFY
  • CE=[CE:16] [CE_INV:0]
  • CK=[CK:16] [CK_INV:0]
  • D=[D:16] [D_INV:0]
  • FFY_INIT_ATTR=[INIT0:16]
  • FFY_SR_ATTR=[SRLOW:16]
  • LATCH_OR_FF=[FF:16]
  • SR=[SR:16] [SR_INV:0]
  • SYNC_ATTR=[SYNC:16]
SLICEL_XORF
  • 1=[1_INV:2] [1:15]
 
Pin Data
BUFGMUX
  • I0=1
  • O=1
  • S=1
BUFGMUX_GCLKMUX
  • I0=1
  • OUT=1
  • S=1
BUFGMUX_GCLK_BUFFER
  • IN=1
  • OUT=1
IBUF
  • I=4
  • PAD=4
IBUF_INBUF
  • IN=4
  • OUT=4
IBUF_PAD
  • PAD=4
IOB
  • O1=8
  • PAD=8
IOB_OUTBUF
  • IN=8
  • OUT=8
IOB_PAD
  • PAD=8
SLICEL
  • BX=2
  • CE=18
  • CIN=15
  • CLK=18
  • COUT=15
  • F1=39
  • F2=39
  • F3=22
  • F4=8
  • G1=34
  • G2=34
  • G3=17
  • G4=5
  • SR=18
  • X=22
  • XQ=17
  • Y=18
  • YQ=16
SLICEL_CYMUXF
  • 0=16
  • 1=16
  • OUT=16
  • S0=16
SLICEL_CYMUXG
  • 0=15
  • 1=15
  • OUT=15
  • S0=15
SLICEL_F
  • A1=39
  • A2=39
  • A3=22
  • A4=8
  • D=39
SLICEL_FFX
  • CE=17
  • CK=17
  • D=17
  • Q=17
  • SR=17
SLICEL_FFY
  • CE=16
  • CK=16
  • D=16
  • Q=16
  • SR=16
SLICEL_G
  • A1=34
  • A2=34
  • A3=17
  • A4=5
  • D=34
SLICEL_XORF
  • 0=17
  • 1=17
  • O=17
SLICEL_XORG
  • 0=16
  • 1=16
  • O=16
 
Tool Usage
Command Line History
  • xst -ise <ise_file>
  • xst -ise <ise_file>
  • ngdbuild -ise <ise_file> -intstyle ise -dd _ngo -nt timestamp -i -p xc3s100e-cp132-4 <fname>.ngc <fname>.ngd
  • map -ise <ise_file> -intstyle ise -p xc3s100e-cp132-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -ise <ise_file> -w -intstyle ise -ol std -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -ise <ise_file> -intstyle ise -v 3 -s 4 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -ise <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s100e-cp132-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s100e-cp132-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
bitgen 1 1 0 0 0 0 0
compxlib 3 3 0 0 0 0 0
map 2 2 0 0 0 0 0
ngdbuild 3 3 0 0 0 0 0
par 2 2 0 0 0 0 0
trce 2 2 0 0 0 0 0
xst 5 5 0 0 0 0 0
 
Project Statistics
PROP_Enable_Message_Filtering=false PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false PROP_PropSpecInProjFile=Store non-default values only
PROP_Simulator=ISim (VHDL/Verilog) PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=HDL PROP_UseSmartGuide=false
PROP_UserConstraintEditorPreference=Text Editor PROP_intProjectCreationTimestamp=2013-05-10T11:34:07
PROP_intWbtProjectID=7541A142F1754D2DA8C1E4A280B88218 PROP_intWbtProjectIteration=1
PROP_intWorkingDirLocWRTProjDir=Same PROP_intWorkingDirUsed=No
PROP_lockPinsUcfFile=changed PROP_selectedSimRootSourceNode_behav=Module|CountingTheWorld
PROP_AutoTop=true PROP_DevFamily=Spartan3E
PROP_DevDevice=xc3s100e PROP_DevFamilyPMName=spartan3e
PROP_DevPackage=cp132 PROP_Synthesis_Tool=XST (VHDL/Verilog)
PROP_DevSpeed=-4 PROP_PreferredLanguage=Verilog
FILE_UCF=1 FILE_VERILOG=1
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFGP=1 NGDBUILD_NUM_FDRE=33 NGDBUILD_NUM_IBUF=3 NGDBUILD_NUM_INV=1
NGDBUILD_NUM_LUT2=34 NGDBUILD_NUM_LUT3=26 NGDBUILD_NUM_LUT4=10 NGDBUILD_NUM_LUT4_D=2
NGDBUILD_NUM_LUT4_L=1 NGDBUILD_NUM_MUXCY=31 NGDBUILD_NUM_OBUF=8 NGDBUILD_NUM_XORCY=33
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=1 NGDBUILD_NUM_FDRE=33 NGDBUILD_NUM_IBUF=3 NGDBUILD_NUM_IBUFG=1
NGDBUILD_NUM_INV=1 NGDBUILD_NUM_LUT2=34 NGDBUILD_NUM_LUT3=26 NGDBUILD_NUM_LUT4=10
NGDBUILD_NUM_LUT4_D=2 NGDBUILD_NUM_LUT4_L=1 NGDBUILD_NUM_MUXCY=31 NGDBUILD_NUM_OBUF=8
NGDBUILD_NUM_XORCY=33
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ifmt=mixed -ofn=<design_top> -ofmt=NGC
-p=xc3s100e-4-cp132 -top=<design_top> -opt_mode=Speed -opt_level=1
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -write_timing_constraints=NO -cross_clock_analysis=NO
-bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100 -verilog2001=YES
-fsm_extract=YES -fsm_encoding=Auto -safe_implementation=No -fsm_style=LUT
-ram_extract=Yes -ram_style=Auto -rom_extract=Yes -shreg_extract=YES
-rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES -async_to_sync=NO
-mult_style=Auto -iobuf=YES -max_fanout=500 -bufg=24
-register_duplication=YES -register_balancing=No -optimize_primitives=NO -use_clock_enable=Yes
-use_sync_set=Yes -use_sync_reset=Yes -iob=Auto -equivalent_register_removal=YES
-slice_utilization_ratio_maxmargin=5