`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   18:31:46 08/28/2009
// Design Name:   HelloSynchronousWorld
// Module Name:   N:/myhome/Teaching/2009_2010/Gateway/HelloWorldSynchronous_Lab3/HelloSynchronousWorldTB.v
// Project Name:  HelloWorldSynchronous_Lab3
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: HelloSynchronousWorld
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module HelloSynchronousWorldTB;

	// Inputs
	reg CLK;
	reg IN;

	// Outputs
	wire OUT;
	wire OUTBAR;

	// Instantiate the Unit Under Test (UUT)
	HelloSynchronousWorld uut (
		.CLK(CLK), 
		.IN(IN), 
		.OUT(OUT), 
		.OUTBAR(OUTBAR)
	);

	initial begin
		CLK = 0;
		forever #100 CLK = ~CLK;
	end
	
	initial begin
		// Initialize Inputs
		IN = 0;

		#50 IN = 1;
		#50 IN = 0;
		#200 IN = 1;
		#200 IN = 0;
		#20 IN = ~IN;
		#20 IN = ~IN;
		#20 IN = ~IN;
		#20 IN = ~IN;
		#20 IN = ~IN;
		#20 IN = ~IN;
		#20 IN = ~IN;
		#20 IN = ~IN;
		#20 IN = ~IN;
		
		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here

	end
      
endmodule

