`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    18:15:36 08/28/2009 
// Design Name: 
// Module Name:    HelloSynchronousWorld 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module HelloSynchronousWorld(
    input CLK,
    input IN,
    output reg OUT,
    output reg OUTBAR
    );

	always@(posedge CLK) begin
		OUT <= IN;
		OUTBAR <= ~IN;
	end
	
endmodule
