CountingInDecimal Project Status (05/10/2013 - 11:37:49)
Project File: CountingInDecimal_Lab9.xise Parser Errors: No Errors
Module Name: CountingInDecimal Implementation State: Programming File Generated
Target Device: xc3s100e-4cp132
  • Errors:
No Errors
Product Version:ISE 14.4
  • Warnings:
6 Warnings (0 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 46 1,920 2%  
Number of 4 input LUTs 64 1,920 3%  
Number of occupied Slices 49 960 5%  
    Number of Slices containing only related logic 49 49 100%  
    Number of Slices containing unrelated logic 0 49 0%  
Total Number of 4 input LUTs 79 1,920 4%  
    Number used as logic 64      
    Number used as a route-thru 15      
Number of bonded IOBs 15 83 18%  
Number of BUFGMUXs 1 24 4%  
Average Fanout of Non-Clock Nets 3.39      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentFri May 10 11:37:10 201306 Warnings (0 new)0
Translation ReportCurrentFri May 10 11:37:16 2013000
Map ReportCurrentFri May 10 11:37:23 2013002 Infos (0 new)
Place and Route ReportCurrentFri May 10 11:37:32 2013002 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentFri May 10 11:37:35 2013006 Infos (3 new)
Bitgen ReportCurrentFri May 10 11:37:42 2013000
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentFri May 10 11:37:42 2013
WebTalk Log FileCurrentFri May 10 11:37:49 2013

Date Generated: 05/10/2013 - 12:04:06