ShiftingTheWorld_Lab4 Project Status
Project File: ShiftingTheWorld_Lab4.ise Implementation State: Programming File Generated
Module Name: ShiftRegister
  • Errors:
No Errors
Target Device: xc3s100e-4cp132
  • Warnings:
1 Warning
Product Version:ISE 11.2
  • Routing Results:
All Signals Completely Routed
Design Goal: Balanced
  • Timing Constraints:
All Constraints Met
Design Strategy: Xilinx Default (unlocked)
  • Final Timing Score:
0 (Setup: 0, Hold: 0) (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 7 1,920 1%  
Number of 4 input LUTs 1 1,920 1%  
Number of occupied Slices 7 960 1%  
    Number of Slices containing only related logic 7 7 100%  
    Number of Slices containing unrelated logic 0 7 0%  
Total Number of 4 input LUTs 1 1,920 1%  
    Number used as Shift registers 1      
Number of bonded IOBs 10 83 12%  
    IOB Flip Flops 1      
Number of BUFGMUXs 1 24 4%  
Average Fanout of Non-Clock Nets 1.88      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentFri 28. Aug 18:42:57 2009000
Translation ReportCurrentFri 28. Aug 18:51:06 2009000
Map ReportCurrentFri 28. Aug 18:51:18 2009002 Infos
Place and Route ReportCurrentFri 28. Aug 18:52:00 200901 Warning4 Infos
Power Report     
Post-PAR Static Timing ReportCurrentFri 28. Aug 18:52:09 2009003 Infos
Bitgen ReportCurrentFri 28. Aug 18:52:16 2009000
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of DateFri 28. Aug 18:45:37 2009

Date Generated: 10/30/2009 - 11:13:48