DecodingTheWorld_Lab8 Project Status (08/30/2009 - 15:16:02)
Project File: DecodingTheWorld_Lab8.ise Implementation State: Programming File Generated
Module Name: DecodingTheWorld
  • Errors:
 
Target Device: xc3s100e-4cp132
  • Warnings:
 
Product Version:ISE 11.2
  • Routing Results:
All Signals Completely Routed
Design Goal: Balanced
  • Timing Constraints:
 
Design Strategy: Xilinx Default (unlocked)
  • Final Timing Score:
0 (Setup: 0, Hold: 0) (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of 4 input LUTs 11 1,920 1%  
Number of occupied Slices 6 960 1%  
    Number of Slices containing only related logic 6 6 100%  
    Number of Slices containing unrelated logic 0 6 0%  
Total Number of 4 input LUTs 11 1,920 1%  
Number of bonded IOBs 19 83 22%  
Average Fanout of Non-Clock Nets 2.67      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints:      
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis Report     
Translation ReportCurrentSun 30. Aug 13:46:02 2009   
Map ReportCurrentSun 30. Aug 13:46:17 2009   
Place and Route ReportCurrentSun 30. Aug 13:47:08 2009   
Power Report     
Post-PAR Static Timing ReportCurrentSun 30. Aug 13:47:23 2009   
Bitgen ReportCurrentSun 30. Aug 13:47:35 2009   
 
Secondary Reports [-]
Report NameStatusGenerated

Date Generated: 08/30/2009 - 15:16:03