`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    19:11:40 08/28/2009 
// Design Name: 
// Module Name:    ShiftRegister 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module ShiftRegister(
    input IN,
    output [7:0] OUT,
    input CLK
    );

	wire [7:0] W;
	
	HelloSynchronousWorld D0 (.CLK(CLK),.IN(IN) , .OUT(W[0]));
	HelloSynchronousWorld D1 (.CLK(CLK),.IN(W[0]),.OUT(W[1]));
	HelloSynchronousWorld D2 (.CLK(CLK),.IN(W[1]),.OUT(W[2]));
	HelloSynchronousWorld D3 (.CLK(CLK),.IN(W[2]),.OUT(W[3]));
	HelloSynchronousWorld D4 (.CLK(CLK),.IN(W[3]),.OUT(W[4]));
	HelloSynchronousWorld D5 (.CLK(CLK),.IN(W[4]),.OUT(W[5]));
	HelloSynchronousWorld D6 (.CLK(CLK),.IN(W[5]),.OUT(W[6]));
	HelloSynchronousWorld D7 (.CLK(CLK),.IN(W[6]),.OUT(W[7]));
	
	
	
	assign OUT = W;
	
	
endmodule
