`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    19:11:40 08/28/2009 
// Design Name: 
// Module Name:    ShiftRegister 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module ShiftRegister(
    input IN,
    output [7:0] OUT,
    input CLK
    );

	wire [8:0] W;
	
	genvar index;
	
	generate 
		for (index = 0; index <8; index = index + 1)
		begin: DTypeInstantiation
			HelloSynchronousWorld D (.CLK(CLK),.IN(W[index]) , .OUT(W[index+1]));
		end
	endgenerate

	
	
	assign OUT = W[8:1];
	assign W[0] = IN;
	
	
	
endmodule
