ShiftRegister Project Status (05/10/2013 - 11:32:52)
Project File: ShiftingManyWorlds_Lab5.xise Parser Errors: No Errors
Module Name: ShiftRegister Implementation State: Synthesized
Target Device: xc3s100e-4cp132
  • Errors:
No Errors
Product Version:ISE 14.4
  • Warnings:
No Warnings
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Device Utilization Summary (estimated values) [-]
Logic UtilizationUsedAvailableUtilization
Number of Slices 16 960 1%
Number of Slice Flip Flops 28 1920 1%
Number of 4 input LUTs 4 1920 0%
Number of bonded IOBs 37 83 44%
Number of GCLKs 1 24 4%
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentFri May 10 11:32:51 2013000
Translation Report     
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of DateSat Aug 29 22:49:38 2009

Date Generated: 05/10/2013 - 11:32:52