DecodingTheWorld_Lab8 Project Status (08/30/2009 - 15:16:02) | |||
Project File: | DecodingTheWorld_Lab8.ise | Implementation State: | Programming File Generated |
Module Name: | DecodingTheWorld |
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Target Device: | xc3s100e-4cp132 |
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Product Version: | ISE 11.2 |
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All Signals Completely Routed |
Design Goal: | Balanced |
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Design Strategy: | Xilinx Default (unlocked) |
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0 (Setup: 0, Hold: 0) (Timing Report) |
Device Utilization Summary | [-] | ||||
Logic Utilization | Used | Available | Utilization | Note(s) | |
Number of 4 input LUTs | 11 | 1,920 | 1% | ||
Number of occupied Slices | 6 | 960 | 1% | ||
Number of Slices containing only related logic | 6 | 6 | 100% | ||
Number of Slices containing unrelated logic | 0 | 6 | 0% | ||
Total Number of 4 input LUTs | 11 | 1,920 | 1% | ||
Number of bonded IOBs | 19 | 83 | 22% | ||
Average Fanout of Non-Clock Nets | 2.67 |
Performance Summary | [-] | |||
Final Timing Score: | 0 (Setup: 0, Hold: 0) | Pinout Data: | Pinout Report | |
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
Timing Constraints: |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | ||||||
Translation Report | Current | Sun 30. Aug 13:46:02 2009 | ||||
Map Report | Current | Sun 30. Aug 13:46:17 2009 | ||||
Place and Route Report | Current | Sun 30. Aug 13:47:08 2009 | ||||
Power Report | ||||||
Post-PAR Static Timing Report | Current | Sun 30. Aug 13:47:23 2009 | ||||
Bitgen Report | Current | Sun 30. Aug 13:47:35 2009 |
Secondary Reports | [-] | ||
Report Name | Status | Generated |