HelloWorldSynchronous_Lab3 Project Status (08/28/2009 - 18:59:31)
Project File: HelloWorldSynchronous_Lab3.ise Implementation State: Programming File Generated
Module Name: HelloSynchronousWorld
  • Errors:
No Errors
Target Device: xc3s100e-4cp132
  • Warnings:
1 Warning (0 new)
Product Version:ISE 11.2
  • Routing Results:
All Signals Completely Routed
Design Goal: Balanced
  • Timing Constraints:
All Constraints Met
Design Strategy: Xilinx Default (unlocked)
  • Final Timing Score:
0 (Setup: 0, Hold: 0) (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
    Number of Slices containing only related logic 0 0 0%  
    Number of Slices containing unrelated logic 0 0 0%  
Number of bonded IOBs 4 83 4%  
    IOB Flip Flops 2      
Number of BUFGMUXs 1 24 4%  
Average Fanout of Non-Clock Nets 1.00      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentFri 28. Aug 18:40:04 2009000
Translation ReportCurrentFri 28. Aug 18:57:50 2009000
Map ReportCurrentFri 28. Aug 18:58:03 2009002 Infos (0 new)
Place and Route ReportCurrentFri 28. Aug 18:58:53 200901 Warning (0 new)2 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentFri 28. Aug 18:59:04 2009003 Infos (0 new)
Bitgen ReportCurrentFri 28. Aug 18:59:13 2009000
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of DateFri 28. Aug 18:34:50 2009

Date Generated: 08/28/2009 - 19:08:14