`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   19:28:41 08/28/2009
// Design Name:   ShiftRegister
// Module Name:   N:/myhome/Teaching/2009_2010/Gateway/ShiftingTheWorld_Lab4/ShiftRegisterTB.v
// Project Name:  ShiftingTheWorld_Lab4
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: ShiftRegister
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module ShiftRegisterTB;

	// Inputs
	reg IN;
	reg CLK;

	// Outputs
	wire [7:0] OUT;

	// Instantiate the Unit Under Test (UUT)
	ShiftRegister uut (
		.IN(IN), 
		.OUT(OUT), 
		.CLK(CLK)
	);

	initial begin
		CLK = 0;
		forever #10 CLK = ~ CLK;
	end
	
	initial begin
		// Initialize Inputs
		IN = 0;
		
		#100 IN = 1;
		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here

	end
      
endmodule

