`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    23:57:46 08/29/2009 
// Design Name: 
// Module Name:    CountingTheWorld 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module CountingTheWorld(
    input CLK,
    input UpDown,
	 input RESET,
	 input COUNT_ENABLE,
    output [7:0] OUT
    );

	reg [24:0] DownCounter;
	reg [7:0] Counter;
	
	always@(posedge CLK) begin
		if(RESET)
		 DownCounter <= 0;
		else begin
			if(COUNT_ENABLE) begin
				if(UpDown) begin
					if(DownCounter == 25000000)
						DownCounter <= 0;
					else
						DownCounter <= DownCounter+1;
				end
				else begin
					if(DownCounter ==0)
						DownCounter <= 25000000;
					else
						DownCounter <= DownCounter-1;
				end
			end
		end
	end
	
	
	always@(posedge CLK) begin	
		if(RESET)
			Counter <= 0;
		else begin
			if(DownCounter == 0) begin
				if(UpDown)
					Counter  <= Counter + 1;
				else
					Counter <= Counter - 1;
			end
		end
	end
			

	
	assign OUT = Counter;

endmodule
