ShiftingManyWorlds_Lab5 Project Status (08/29/2009 - 23:30:39)
Project File: ShiftingManyWorlds_Lab5.ise Implementation State: Synthesized
Module Name: ShiftRegister
  • Errors:
No Errors
Target Device: xc3s100e-4cp132
  • Warnings:
No Warnings
Product Version:ISE 11.2
  • Routing Results:
 
Design Goal: Balanced
  • Timing Constraints:
 
Design Strategy: Xilinx Default (unlocked)
  • Final Timing Score:
  
 
Device Utilization Summary (estimated values) [-]
Logic UtilizationUsedAvailableUtilization
Number of Slices 16 960 1%
Number of Slice Flip Flops 28 1920 1%
Number of 4 input LUTs 4 1920 0%
Number of bonded IOBs 37 83 44%
Number of GCLKs 1 24 4%
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentSat 29. Aug 22:32:52 2009000
Translation Report     
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogCurrentSat 29. Aug 22:49:39 2009

Date Generated: 10/30/2009 - 11:14:04