`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    19:11:40 08/28/2009 
// Design Name: 
// Module Name:    ShiftRegister 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module ShiftRegister(
    input IN,
    output [7:0] OUT,
    input CLK
    );

	reg [7:0] DTypes;

/// ONE WAY OF DOING SHIFT BEHAVIOURALLY
//	always@(posedge CLK) begin
//		DTypes[7] <= DTypes[6];
//		DTypes[6] <= DTypes[5];
//		DTypes[5] <= DTypes[4];
//		DTypes[4] <= DTypes[3];
//		DTypes[3] <= DTypes[2];
//		DTypes[2] <= DTypes[1];
//		DTypes[1] <= DTypes[0];
//		DTypes[0] <= IN;
//	end
//	
//	
//	assign OUT = DTypes;
	
/// SECOND WAY OF DOING SHIFT BEHAVIOURALLY
//	always@(posedge CLK) 
//		DTypes <= (DTypes[6:0], IN);
//	
//	
//	assign OUT = DTypes;	
	
endmodule
