CountingTheWorld_Lab6 Project Status (08/30/2009 - 00:25:23)
Project File: CountingTheWorld_Lab6.ise Implementation State: Programming File Generated
Module Name: CountingTheWorld
  • Errors:
No Errors
Target Device: xc3s100e-4cp132
  • Warnings:
1 Warning (0 new)
Product Version:ISE 11.2
  • Routing Results:
All Signals Completely Routed
Design Goal: Balanced
  • Timing Constraints:
All Constraints Met
Design Strategy: Xilinx Default (unlocked)
  • Final Timing Score:
0 (Setup: 0, Hold: 0) (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 8 1,920 1%  
Number of 4 input LUTs 8 1,920 1%  
Number of occupied Slices 4 960 1%  
    Number of Slices containing only related logic 4 4 100%  
    Number of Slices containing unrelated logic 0 4 0%  
Total Number of 4 input LUTs 8 1,920 1%  
Number of bonded IOBs 10 83 12%  
Number of BUFGMUXs 1 24 4%  
Average Fanout of Non-Clock Nets 2.33      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentSun 30. Aug 00:03:43 2009000
Translation ReportCurrentSun 30. Aug 00:23:17 2009000
Map ReportCurrentSun 30. Aug 00:23:36 2009002 Infos (0 new)
Place and Route ReportCurrentSun 30. Aug 00:24:38 200901 Warning (0 new)4 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentSun 30. Aug 00:24:50 2009003 Infos (0 new)
Bitgen ReportCurrentSun 30. Aug 00:25:02 2009000
 
Secondary Reports [-]
Report NameStatusGenerated

Date Generated: 08/30/2009 - 00:31:04