ShiftingTheWorld_Lab4 Project Status
Project File: | ShiftingTheWorld_Lab4.ise | Implementation State: | Programming File Generated
Module Name: | ShiftRegister | Errors: | No Errors
Target Device: | xc3s100e-4cp132 | Warnings: | 1 Warning
Product Version: | ISE 11.2 | Routing Results: | All Signals Completely Routed
Design Goal: | Balanced | Timing Constraints: | All Constraints Met
Design Strategy: | Xilinx Default (unlocked) | Final Timing Score: | 0 (Setup: 0, Hold: 0) (Timing Report)

Device Utilization Summary | [-]
Logic Utilization | Used | Available | Utilization | Note(s)
Number of Slice Flip Flops | 7 | 1,920 | 1% |
Number of 4 input LUTs | 1 | 1,920 | 1% |
Number of occupied Slices | 7 | 960 | 1% |
Number of Slices containing only related logic | 7 | 7 | 100% |
Number of Slices containing unrelated logic | 0 | 7 | 0% |
Total Number of 4 input LUTs | 1 | 1,920 | 1% |
Number used as Shift registers | 1 |  |  |
Number of bonded IOBs | 10 | 83 | 12% |
IOB Flip Flops | 1 |  |  |
Number of BUFGMUXs | 1 | 24 | 4% |
Average Fanout of Non-Clock Nets | 1.88 |  |  |

Performance Summary | [-]
Final Timing Score: | 0 (Setup: 0, Hold: 0) | Pinout Data: | Pinout Report
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report
Timing Constraints: | All Constraints Met |  |

Detailed Reports | [-]
Report Name | Status | Generated | Errors | Warnings | Infos
Synthesis Report | Current | Fri 28. Aug 18:42:57 2009 | 0 | 0 | 0
Translation Report | Current | Fri 28. Aug 18:51:06 2009 | 0 | 0 | 0
Map Report | Current | Fri 28. Aug 18:51:18 2009 | 0 | 0 | 2 Infos
Place and Route Report | Current | Fri 28. Aug 18:52:00 2009 | 0 | 1 Warning | 4 Infos
Power Report |  |  |  |  |
Post-PAR Static Timing Report | Current | Fri 28. Aug 18:52:09 2009 | 0 | 0 | 3 Infos
Bitgen Report | Current | Fri 28. Aug 18:52:16 2009 | 0 | 0 | 0

Secondary Reports | [-]
Report Name | Status | Generated
ISIM Simulator Log | Out of Date | Fri 28. Aug 18:45:37 2009

Date Generated: 10/30/2009 - 11:13:48