ColouringTheWorld_Lab10 Project Status (09/26/2009 - 19:45:54)
Project File: ColouringTheWorld_Lab10.ise Implementation State: Programming File Generated
Module Name: ColouringTheWorld
  • Errors:
No Errors
Target Device: xc3s100e-4cp132
  • Warnings:
4 Warnings (0 new)
Product Version:ISE 11.2
  • Routing Results:
All Signals Completely Routed
Design Goal: Balanced
  • Timing Constraints:
All Constraints Met
Design Strategy: Xilinx Default (unlocked)
  • Final Timing Score:
0 (Setup: 0, Hold: 0) (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 42 1,920 2%  
Number of 4 input LUTs 99 1,920 5%  
Number of occupied Slices 71 960 7%  
    Number of Slices containing only related logic 71 71 100%  
    Number of Slices containing unrelated logic 0 71 0%  
Total Number of 4 input LUTs 124 1,920 6%  
    Number used as logic 99      
    Number used as a route-thru 25      
Number of bonded IOBs 27 83 32%  
Number of BUFGMUXs 1 24 4%  
Average Fanout of Non-Clock Nets 2.71      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentSat 26. Sep 19:48:32 200904 Warnings (0 new)1 Info (0 new)
Translation ReportCurrentSat 26. Sep 19:48:53 2009000
Map ReportCurrentSat 26. Sep 19:49:09 2009002 Infos (0 new)
Place and Route ReportCurrentSat 26. Sep 19:50:02 2009004 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentSat 26. Sep 19:50:15 2009003 Infos (0 new)
Bitgen ReportCurrentSat 26. Sep 19:50:28 2009000
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of DateSun 30. Aug 23:04:20 2009

Date Generated: 09/30/2009 - 11:49:09