`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    23:57:46 08/29/2009 
// Design Name: 
// Module Name:    CountingTheWorld 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module CountingTheWorld(
    input CLK,
    input UpDown,
    output reg [7:0] OUT
    );

	always@(posedge CLK) begin
		if(UpDown)
		 OUT <= OUT + 1;
		else
		 OUT <= OUT - 1;
	end

endmodule
