TimingTheWorld_Lab7 Project Status (08/30/2009 - 00:53:26)
Project File: TimingTheWorld_Lab7.ise Implementation State: Programming File Generated
Module Name: CountingTheWorld
  • Errors:
No Errors
Target Device: xc3s100e-4cp132
  • Warnings:
No Warnings
Product Version:ISE 11.2
  • Routing Results:
All Signals Completely Routed
Design Goal: Balanced
  • Timing Constraints:
All Constraints Met
Design Strategy: Xilinx Default (unlocked)
  • Final Timing Score:
0 (Setup: 0, Hold: 0) (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 33 1,920 1%  
Number of 4 input LUTs 73 1,920 3%  
Number of occupied Slices 39 960 4%  
    Number of Slices containing only related logic 39 39 100%  
    Number of Slices containing unrelated logic 0 39 0%  
Total Number of 4 input LUTs 73 1,920 3%  
Number of bonded IOBs 12 83 14%  
Number of BUFGMUXs 1 24 4%  
Average Fanout of Non-Clock Nets 3.18      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentSun 30. Aug 00:46:07 2009000
Translation ReportCurrentSun 30. Aug 00:51:20 2009000
Map ReportCurrentSun 30. Aug 00:51:35 2009002 Infos (0 new)
Place and Route ReportCurrentSun 30. Aug 00:52:41 2009004 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentSun 30. Aug 00:52:59 2009003 Infos (0 new)
Bitgen ReportCurrentSun 30. Aug 00:53:12 2009000
 
Secondary Reports [-]
Report NameStatusGenerated

Date Generated: 08/30/2009 - 00:53:27