`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    19:11:40 08/28/2009 
// Design Name: 
// Module Name:    ShiftRegister 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module ShiftRegister(
    input [3:0] IN,
    output [3:0] OUT0,
    output [3:0] OUT1,
    output [3:0] OUT2,
    output [3:0] OUT3,
    output [3:0] OUT4,
    output [3:0] OUT5,
    output [3:0] OUT6,
    output [3:0] OUT7,
    input CLK
    );

	reg [3:0] DTypes[7:0];
	
	always@(posedge CLK)  begin
		DTypes[0] <= IN;
		DTypes[1] <= DTypes[0];
		DTypes[2] <= DTypes[1];
		DTypes[3] <= DTypes[2];
		DTypes[4] <= DTypes[3];
		DTypes[5] <= DTypes[4];
		DTypes[6] <= DTypes[5];
		DTypes[7] <= DTypes[6];
	end
	
	
	assign OUT0 = DTypes[0];	
	assign OUT1 = DTypes[1];	
	assign OUT2 = DTypes[2];	
	assign OUT3 = DTypes[3];	
	assign OUT4 = DTypes[4];	
	assign OUT5 = DTypes[5];	
	assign OUT6 = DTypes[6];	
	assign OUT7 = DTypes[7];	
	
	
	
endmodule
