`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   16:45:53 08/28/2009
// Design Name:   HelloWorld
// Module Name:   N:/myhome/Teaching/2009_2010/Gateway/HellowWorld_Lab1/HellowWorld.v
// Project Name:  HellowWorld_Lab1
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: HelloWorld
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module HellowWorld;

	// Inputs
	reg IN;

	// Outputs
	wire OUT;

	// Instantiate the Unit Under Test (UUT)
	HelloWorld uut (
		.IN(IN), 
		.OUT(OUT)
	);

	initial begin
		// Initialize Inputs
		IN = 0;

		#500 IN = 1;
		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here

	end
      
endmodule

