DecodinTheWorldTop Project Status (05/10/2013 - 11:36:48)
Project File: | DecodingTheWorld_Lab8.xise | Parser Errors: | No Errors
Module Name: | DecodinTheWorldTop | Implementation State: | Programming File Generated
Target Device: | xc3s100e-4cp132 | Errors: | No Errors
Product Version: | ISE 14.4 | Warnings: | No Warnings
Design Goal: | Balanced | Routing Results: | All Signals Completely Routed
Design Strategy: | Xilinx Default (unlocked) | Timing Constraints: |
Environment: | System Settings | Final Timing Score: | 0 (Timing Report)

Device Utilization Summary | [-]
Logic Utilization | Used | Available | Utilization | Note(s)
Number of 4 input LUTs | 7 | 1,920 | 1% |
Number of occupied Slices | 4 | 960 | 1% |
Number of Slices containing only related logic | 4 | 4 | 100% |
Number of Slices containing unrelated logic | 0 | 4 | 0% |
Total Number of 4 input LUTs | 7 | 1,920 | 1% |
Number of bonded IOBs | 16 | 83 | 19% |
Average Fanout of Non-Clock Nets | 3.18 |  |  |

Performance Summary | [-]
Final Timing Score: | 0 (Setup: 0, Hold: 0) | Pinout Data: | Pinout Report
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report
Timing Constraints: |  |  |

Detailed Reports | [-]
Report Name | Status | Generated | Errors | Warnings | Infos
Synthesis Report | Current | Fri May 10 11:35:38 2013 | 0 | 0 | 0
Translation Report | Current | Fri May 10 11:35:46 2013 | 0 | 0 | 0
Map Report | Current | Fri May 10 11:35:52 2013 | 0 | 0 | 2 Infos (0 new)
Place and Route Report | Current | Fri May 10 11:35:59 2013 | 0 | 0 | 1 Info (0 new)
Power Report |  |  |  |  |
Post-PAR Static Timing Report | Current | Fri May 10 11:36:01 2013 | 0 | 0 | 6 Infos (3 new)
Bitgen Report | Current | Fri May 10 11:36:40 2013 | 0 | 0 | 0

Secondary Reports | [-]
Report Name | Status | Generated
WebTalk Report | Current | Fri May 10 11:36:40 2013
WebTalk Log File | Current | Fri May 10 11:36:48 2013

Date Generated: 05/10/2013 - 11:36:48