Tobi Delbruck
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2-d motion chip

This page holds a paper about a 2-d analog motion chip.

T. Delbrück. (1993). Silicon retina with Correlation-Based, Velocity-Tuned Pixels. IEEE Transactions on Neural Networks, Vol. 4, No. 3, pp. 529–541.

In this paper, I discuss a two-dimensional silicon retina that computes a complete set of local direction-selective outputs. The chip motion computation uses unidirectional delay lines as tuned filters for moving edges. The motion computation is based on the Reichardt correlation detector, but has been extended to over a wider spatial and temporal range, as shown here:

Photoreceptors detect local changes in image intensity, and the outputs from these photoreceptors are coupled into the delay line, where they propagate with a particular speed in one direction. If the velocity of the moving edges matches that of the delay line, then the signal on the delay line is reinforced. The output of each pixel is the power in the delay line signal, computed within each pixel. This power computation provides the essential nonlinearity for velocity-selectivity. Here is what part of the circuit within each pixel looks like:

The delay line architecture differs from the usual pairwise correlation models in that motion information is aggregated over an extended spatiotemporal range. As a result, the detectors are sensitive to motion over a wide range of spatial frequencies.

In two dimensions, I have used a hexagonal architecture, as shown here: Architecture

The directional tuning at a particular spatial frequency and speed of the three outputs from a pixel look like this:

In response to some moving patterns, the chip output which is displayed on a monitor in real time, looks like this:

I have designed and tested functional one- and two-dimensional silicon retinas with direction-selective, velocity-tuned pixels. A velocity-selective detector requires only a single delay element and nonlinearity for each tuned velocity, and is sensitive to both light and dark contrasts. The use of adaptive photoreceptors and compact circuits makes for a well-conditioned input signal and small circuit offsets, resulting in robust operation. All circuits work in subthreshold, resulting in low power consumption. Pixels with three hexagonal directions of motion selectivity are approximately (225 µm)^2 area in a 2-µm CMOS technology, and consume less than 5 µW of power.

Some of the circuits used in this pixel are described in papers. The receptor circuits are discussed here. The antibump nonlinearity circuit is discussed here. The scanner used to visualize the activity of this (and other) chip(s) is discussed here.

Ron Benson, Carver Mead, and I developed a related (or complementary) approach that uses null-inhibition instead of correlation to make directive selective, velocity-tuned responses.

Tobi Delbruck

September 13, 2007
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