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Understanding Spike Toolbox addressing
Introduction to addressingAddressing fieldsLogical and Hardware addressesPassing addresses and addressing schemes as argumentsUtility functions for addressing specificationsSetting default addressing schemesChannel address specificationsManually designing an addressing specification
Introduction to addressing
In designing the spike toolbox, we realise that we can't predict the types of systems you might want to simulate or stimulate with it. Chips communicating over spike-based busses can have arbitrary numbers, types and dimensions of addresses you might want to associate with a spike. More abstract simulation systems might be even more esoteric.
For this reason, the toolbox supports arbitrary addressing schemes. Any number of fields of neurons and synapses are supported, as well as built-in range checking and conversion to binary hardware addresses. However, this flexibility brings with it some complications in the configuration of the toolbox for a particular addressing scheme. This topic covers all you need to know about setting up any particular addressing scheme and using it to map spike trains.
Addressing fields
A toolbox address is composed of one or more fields. A field encapsulates a single addressing dimension, such as a neuron address (or an X, Y, Z etc. component of a neuron address) or a synapse address (ditto). When providing a full address to the toolbox, a field index must be provided for each field not set to be ignored. Any number of fields may be defined in an addressing specification.
The interpretation of an address field is arbitrary; fields can (and should) be assigned names meaningful to the user, but the toolbox doesn't care. However, a field can arbitrarily be marked major or minor. This flag has relevence when the toolbox creates logical addresses, described below. As mentioned above, fields can be assigned an arbitrary maximum value, and be automatically range checked whenever an addressing operation is performed.
An addressing field is a simple MATLAB structure, with field names as deescribed below. When defining a field, the following information is required:
nWidth - The width of a field in bits.Description - A textual representation of what the field means.bMajorField - This flag is used when constructing logical addresses. If a field is marked as major it will be a primary component in constructing a logical address. For example, neuron addressing fields might be considered major, while synapse addressing fields might be considered minor. See below for more information on logical addresses.bIgnore - A flag indicating that the addressing field should be ignored. A field marked ignore will not be required by the toolbox when passing a full address as an argument. This field can be used to mark off unused bits in a binary address.bRangeCheck - Along with nMax, defines whether an addressing field should be automatically range-checked by the toolbox. An error will be printed when an addressing index falls outside the defined range: the full address will be considered invalid by the toolbox.nMax - Defines the maximum allowable index for the addressing field. Note that if a field is 8 bits then 255 is automatically taken as the maximum index for that field, if nMax is not defined. nMax is useful when there are actually only 234 neurons in the array.bInverse - The bits in this addressing field will be negated (inverted) when constucting a binary (hardware) address.bReverse - The bits in this addressing field will be reversed (most-significant and least-significant bits will be swapped) when constructing a binary address.
Logical and Hardware addresses
When displaying raster plots and other information to the user, it is helpful to be able to present a full complex address as a single decimal number. This is called a logical address. To perform this conversion, the toolbox groups addressing fields together based on the major or minor flag, described above.
Major fields are combined and placed on the left of a decimal point. Minor fields are placed on the right of the decimal point. The least to most significant order of the fields is maintained within each group. Fields are combined according to the number of bits each field occupies, as specified by the addressing specification.
Here is an example of constructing a logical address: For our addressing scheme, we will have a neuron and a synapse address of four bits each. The neuron address will be least significant, and will be marked as a major field. The synapse address will be marked as a minor field.
|(7) Synapse (4)|(3) Neuron (0)|
For a full address of (4, 2) (ie a neuron address of 4 and a synapse address of 2), we will simply take the neuron field and place it left of a decimal point, since it is the only major field. The synapse field will be shifted right by four bits, and placed to the right of the decimal point (ie 2 becomes 0.125).
(4, 2) --> (addressing specification) --> 4.125
Hardware addresses
Harware addresses are conceptually more simple. They simply transform each address index into binary according to the addressing specification, arrange the fields in the specified order and output a binary number.
For the example above, (4, 2) --> (addressing specification) --> 00100100 (0x24).
Passing addresses and addressing schemes as arguments
When addresses are passed as arguments to the toolbox, they are always written as a fully qualified address. Each address index is supplied in least-to most-significant field order as a separate argument. For most functions that accept an address, and addressing specification can be supplied as an argument, as part of the address. The exception is when manipulating a spike train which already contains an addressing specification. All mapped spike trains contain a copy of the addressing specification used to create the mapping. See the documentation for individual toolbox functions to check their calling syntax.
Example: stMapped = STMap(stInstantiated, 4, 2);
Using our example addressing scheme above and our example address (4, 2), this will map a spike train to neuron 4, synapse 2.
Addressing schemes themselves are encapsulated in a toolbox stasSimple, then
stMapped = STMap(stInstantiated, 4, 2, stasSimple);
will map stInstantiated according to our scheme.
Utility functions for addressing specifications
Most basic addressing schemes have specific toolbox functions to create a paramaterised addressing specification. This eases the process of designing an addressing specification manually. These utility functions return a pre-made specification object, which can be modified if necessary. Here we will describe one of these functions; for a full list, see the categorical function index.
[stasSpecification] = ...
STAddrSpecIgnoreNeuronSynapse(nIgnoreBits, nNeuronBits, nSynapseBits)
[stasSpecification] = ...
STAddrSpecIgnoreNeuronSynapse(nIgnoreBits, nNeuronBits, nSynapseBits, ...
nNeuronMax, nSynapseMax, ...
bInvertNeuron, bInvertSynapse)
STAddrSpecIgnoreNeuronSynapse will return a specification for an addressing scheme with (optionally) three fields; a number of ignored bits, a number of bits for a neuron address and a number of bits for a synapse address. Any of these three fields are optional, and can be removed from the specification by providing 0 for one of the width arguments. The two functional fields can optionally be inverted and range-checked.
Considering again our simple addressing scheme above,
stasSimple = STAddrSpecIgnoreNeuronSynapse(0, 4, 4);
will be sufficient to construct a corresponding addressing specification.
Setting default addressing schemes
For detailed information on setting options for the toolbox and making them persistent, see Managing spike toolbox options. This topic assumes you know how to obtain, modify and set a spike toolbox options structure.
The toolbox options allow you to set a default output addressing specification (which will be used by default when mapping spike trains), and several monitor channel addressing specifications which will be used when monitoring spike trains with STStimulate. Within the toolbox options structure, the following fields relate to addressing shemes:
stasDefaultOutputSpecification - This addressing specifcation object sets the default output addressing scheme used when mapping spike trains.MonitorChannelsAddressing - This cell array of addressing specification objects defines not only which monitor channels to import by default when monitoring with STStimulate, but also the addressing schemes to apply to spikes arising from those channels.stasMonitorChannelID - This addressing specification object defines which bits of the hardware spike address coming from the AER bus specify the channel address. Channel addressing specifications are described in detail below.
Channel address specifications
Channel addressing specifications are a restricted type of addressing specification, used to identify which bits in an address relate to the monitor channel ID. A channel address must contain two fields only, the first with bIgnore set. The second field will define the channel ID address bits. As always, there's a utility function STAddrSpecChannel to help you.
[stasSpecification] = STAddrSpecChannel(nIgnoreBits, nChannelBits)
[stasSpecification] = STAddrSpecChannel(nIgnoreBits, nChannelBits, bInvert)
Manually designing an addressing specification
Spike toolbox addressing specification objects are MATLAB structure arrays, containing only the fields described above. Each address field is a separate array element, in order from least- to most-significant field. We recommend that you use the utility functions supplied to quickly create specification structures, but creating your own should be relatively easy if the utility functions do not suffice.
[bValid] = STIsValidAddress(nAddr1, nAddr2, ...)
[bValid] = STIsValidAddress(stasSpecification, nAddr1, nAddr2, ...)
[bValid] = STIsValidAddrSpec(stasSpecification)
[bValid] = STIsValidChannelAddrSpec(stasChannelSpec)
Our simple address specification from above looks like this:
stasSimple =
1x2 struct array with fields:
Description
nWidth
bReverse
bInvert
bMajorField
bRangeCheck
bIgnore
stasSimple(1) =
Description: 'Neuron address'
nWidth: 4
bReverse: 0
bInvert: 0
bMajorField: 1
bRangeCheck: 0
bIgnore: 0
stasSimple(2) =
Description: 'Synapse address'
nWidth: 4
bReverse: 0
bInvert: 0
bMajorField: 0
bRangeCheck: 0
bIgnore: 0
STDescribe is your friend as always, especially when creating an addressing specification from scratch. STDescribe will pretty-print an addressing specification in a user-friendly format.
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Configuring the toolbox
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Spike train levels
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